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fn8091 rev 3.00 page 1 of 17 march 31, 2011 fn8091 rev 3.00 march 31, 2011 isl21400 programmable temperature slope voltage reference datasheet the isl21400 features a pre cision voltage reference combined with a temp erature sensor whose output voltage varies linearly with temperat ure. the precision 1.20v reference has a very low temperature coefficient (tempco), and its output voltage is scaled by an internal dac (v ref ) to produce a temperat ure stable output voltage that is programmable from 0v to 1.20v. the output voltage from the temperature sensor (v ts ) is summed with v ref to produce a temperature depend ent output voltage. the slope of the v ts portion of the output voltage can be programmed to be positive or nega tive in the range -2.1mv/c to +2.1mv/c. a programmable gain amplifier (pga) sums the v ts and the v ref voltages and provides gains of 1x, 2x, and 4x to scale the output up to 4.8v and the slope to 8.4mv/c. the v ref and v ts terms are programmabl e with 8 bits of resolution via an i 2 c bus and the values are stored in non-volatile registers. the pg a gain is also set via the i 2 c bus and the value is stored in a non-volatile register. non-volatile memory stora ge assures the programmed settings are retained on power-down, eliminating the need for software initializat ion at device power-up. temperature characteristics curve features ? programmable reference voltage ? programmable temperature slope ? programmable gain amplifier ? non-volatile storage o f programming registers ?i 2 c serial interface ? 2% total accuracy ov er temperature and v cc range ? 200a typical active supply current ? operating temperature range = -40c to +85c ? 8 ld msop package ? pb-free (rohs compliant) applications ? rf power amplifier bias compensation ? lcd bias compensation ? laser diode bias compensation ? sensor bias and linearization ? data acquisition systems ? variable dac reference ? amplifier biasing pinout isl21400 (8 ld msop) top view 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -15 10 35 60 85 temperature (c) v ref (v) ts = 0 ts = 255 ts = 127 ts = 0 ts = 127 ts = 255 a v = 2 a v = 1 pin descriptions msop symbol description 1 a2 hardwire slave address pin for i 2 c serial bus 2 a1 hardwire slave address pin for i 2 c serial bus 3 a0 hardwire slave address pin for i 2 c serial bus 4v ss ground pin 5 scl serial bus clock input 6 sda serial bus data input/output 7 vout output voltage 8v cc device power supply a2 v cc 1 2 3 4 sda scl 8 7 6 5 a0 v out v ss a1
isl21400 fn8091 rev 3.00 page 2 of 17 march 31, 2011 block diagram ordering information part number (note 3) part marking v dd range (v) temp range (c) package (pb-free) pkg. dwg. # isl21400iu8z (note 2) dew 2.7 to 5.5 -40 to +85 8 ld msop (3.0mm), green mtl m8.118 isl21400iu8z-tk (notes 1, 2) dew 2.7 to 5.5 -40 to +85 8 ld msop (3 .0mm), green mtl m8.118 ISL21400USB-EVALZ evaluation board 1. please refer to tb347 for det ails on reel s pecifications. 2. these intersil pb-free plasti c packaged products employ speci al pb-free material sets, molding compounds/die attach material s, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device infor mation page for isl21400 . for more information on msl please see techbrief tb363 . vcc temp sense v ref (m) bias communications 5 bytes and registers eeprom scl sda gain select av = 1, 2, 4 v out a0 a1 a2 vss dac dac a s n = 0 to 255 m = 0 to 255 v ts (n) v ref
isl21400 fn8091 rev 3.00 page 3 of 17 march 31, 2011 absolute maximum ratings thermal information supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 6.5v voltage on v out pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to v cc voltage on all other pins . . . . . . . . . . . . . . . . . . - 0.3v to v cc +0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v thermal resistance (typical) ? ja (c/ w) 8 ld msop package (note 4) . . . . . . . . . . . . . . . . . 13 0 moisture sensitivity for msop package (see technical brief tb363) . . . . . . . . . . . . . . . . . . . . . . . level 2 maximum junction temperat ure (plastic package). . . . . . . . +1 50c storage temperature range . . . . . . . . . . . . . . . . . .-6 5c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in fr ee air. see tech bried tb379 for details. analog specifications v cc = 5.5v, t a = +25c to +85c, unless otherwise noted. symbol parameter test conditions min typ (note 6) max units power supply v cc supply voltage range 2.7 3.0 5.5 v i q supply v cc = 2.7v standby, sda = scl = v cc 200 400 a v cc = 5.5v standby, sda = scl = v cc 235 500 a i q(nv) non-volatile supply v cc = 2.7v nonvolatile write 500 750 a v cc = 5.5v nonvolatile write 1.3 1.6 ma vpor power-on recall voltage minimum v cc at which memory recall occurs 2.0 2.6 v v cc ramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, time delay to register recall, and i 2 c interface in standby state 3ms output voltage performance specifications g e1 gain error a v = 2 (notes 5, 6, 15) -1 +1 % g e2 gain error a v = 4 (notes 5, 6, 15) -1 +1 % k temperature sensor coefficient (notes 5, 12) -2.2 -2.1 -2.0 mv/c absolute output voltage (swing) range unloaded, t a = +25c (note 7) v cc - 0.100 gnd + 0.100 v absolute output voltage (swing) range loaded, i out = 500a (note 7) v cc - 0.250 gnd + 0.250 v ts1 temperature sensor slope a v = 1, n = 255, m = 255 (notes 5, 9) -2.1 mv/c ts2 temperature sensor slope a v = 2, n = 255, m = 255 (notes 5, 9) -4.2 mv/c ts3 temperature sensor slope a v = 4, n = 255, m = 255 (notes 5, 9) -8.4 mv/c
isl21400 fn8091 rev 3.00 page 4 of 17 march 31, 2011 ts4 incremental temperature sensor slope a v = 1, n = 255, m = 0 to 255 (notes 5, 13) 8.2 v/c per code tsnl temperature slope non-linearity n = 255, m = 0 to 255, t = - 40c to +85c (notes 5, 14) 0.5 1.0 % dnl dac relative linearity (v cc = 2.7 to 5.5v) v ref and temp sense; a v = 1 (note 17) -1.0 +1.0 lsb inl dac absolute linearity (v cc = 2.7 to 5.5v) v ref and temp sense; a v = 1 (note 17) -3.0 +3.0 lsb v out(te) total error for v out (notes 5, 11, 12) 1 2 % v out1 output voltage v ref , gain = 1 a v = 1, n = 255, m = 128, t a = +25c, v cc =5.5v 1.189 1.2 1.211 v v out2 output voltage v ref , gain = 2 a v = 2, n = 255, m = 128, t a = +25c, v cc =5.5v 2.378 2.40 2.422 v v out3 output voltage v ref , gain = 4 a v = 4, n = 255, m = 128, t a = +25c, v cc =5.5v 4.756 4.80 4.844 v v out4 output voltage v ref + ts a v = 1, n = 255, m = 0, t a = +85c (note 7) 1.315 1.326 1.337 v v out5 output voltage v ref + ts a v = 1, n = 255, m = 128, t a = +85c (note 7) 1.188 1.199 1.210 v v out6 output voltage v ref + ts a v = 1, n = 255, m = 255, t a = +85c (note 7) 1.063 1.074 1.085 v v out7 output voltage v ref + ts a v = 1, n = 255, m = 0, t a =-40c, (note 7) 1.052 1.063 1.074 v v out8 output voltage v ref + ts a v = 1, n = 255, m = 128, t a = -40c, (note 7) 1.189 1.200 1.211 v v out9 output voltage v ref + ts a v = 1, n = 255, m = 255, t a = -40c, (note 7) 1.336 1.325 1.347 v output voltage dc specifications psrr power supply rejection ratio a v = 1, n = 255, m = 128, (note 10) 50 60 db r out output impedance (load regulation) given by r out = ( ? v out / ? i out ), t a = +25c, i out = 500a 25 ? i sc short circuit, sourcing v cc = 5.5v, v out = 0v 5 9 ma short circuit, sinking v cc = 5.5v, v out = 5.5v 6 9 ma c l load capacitance reference output stable for all c l up to specifications 5nf output voltage ac specifications v n output voltage noise 0.1hz to 10hz, a v =1 90 v p-p 10hz to 10khz, c l = 0, a v = 1 tbd mv rms power-on response 1% settling 500 s line ripple rejection v cc = 5v 100mv, f = 120hz 60 db analog specifications v cc = 5.5v, t a = +25c to +85c, unless otherwise noted. (continued) symbol parameter test conditions min typ (note 6) max units
isl21400 fn8091 rev 3.00 page 5 of 17 march 31, 2011 serial interface specification for scl, sda, a0, a1, a2 unless otherwise noted. symbol parameter test conditions min typ (note 2) max units i li input leakage v in = gnd to v cc 1v v il input low voltage -0.3 0.3 x v cc v v ih input high voltage 0.7 x v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v cc v v ol sda output buffer low voltage i ol = 3ma 0 0.4 v c pin pin capacitance (note 7) 10 pf f scl scl frequency (note 7) 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed (note 7) 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window (note 7) 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition (note 7) 1300 ns t low clock low time measured at the 30% of v cc crossing (note 7) 1300 ns t high clock high time measured at the 70% of v cc crossing (note 7) 600 ns t su:sta start condition set-up time scl rising edge to sda falling edge; both crossing 70% of v cc (note 7) 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc (note 7) 600 ns t su:dat input data set-up time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc (note 7) 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window (note 7) 0ns t su:sto stop condition set-up time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc (note 7) 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing 70% of v cc (note 7) 1300 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window (note 7) 0ns t r sda and scl rise time from 30% to 70% of v cc (note 7) 20 + 0.1 x cb 250 ns
isl21400 fn8091 rev 3.00 page 6 of 17 march 31, 2011 t f sda and scl fall time from 70% to 30% of v cc (note 7) 20 + 0.1 x cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip (note 7) 10 400 pf rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ? ~2.5k ? for cb = 40pf, max is about 15k ? ~20k ? 1k ? i lo output leakage current (sda only) v out = gnd to v cc 1a v il a1, a0, shdn , sda, and scl input buffer low voltage -0.3 v cc x 0.3 v v ih a1, a0, shdn , sda, and scl input buffer high voltage v cc x 0.7 v cc v v ol sda output buffer low voltage i ol = 100a (note 7), at 3ma sink 00.4v c l capacitive loading of sda or scl total on-chip and off-chip (note 7) 10 400 pf eeprom endurance 1,000,000 cycles eeprom retention temperature t ? +55c 50 years t wc (note 18) non-volatile write cycle time 12 20 ms notes: 5. equation 1 governs the output voltage and is stated as follow s: 6. typical values are for t a = +25c and v cc = 5.5v. 7. this parameter is not 100% tested. 8. cb = total capacitance of one bus line in pf. 9. t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-ti med internal nonvolatile writ e cycle. it is the minimum cycle time to be allowed for any nonvolatile write by t he user. 10. over the specified temperature range. temperature slope (ts) is measured by the box method whereby the change in v out is divided by the temperature range; in this case, -40c to +85c = +125c. ts 1 , ts 2 , ts 3 = 11. given by psrr (db) = 20 * log 10 ( ? vout/ ? v cc ) at dc. 12. test +25c and +85c only. 13. total error of equation 1 @ a v = 1, k = -2.1mv/c, v ref = 1.20v, m = 255, n = 255 to 0, v cc = 3.0v. 14. over the specified temperature range. temperature slope (ts ) is measured by the box method whereby the change in v out is divided by the temperature range. incremental ts is the temperature slope at m = 255 minus the temperature slope at m = 0 divided by 255 with a v = 1, n = 255 serial interface specification for scl, sda, a0, a1, a2 unless otherwise noted. (continued) symbol parameter test conditions min typ (note 2) max units v out a v v ref n 255 --------- - ? kt t 0 C ?? 2m ? ?? 255 C 255 -------------------------------- + ?? ?? ?? ? n = 0 to 255, m = 0 to 255, k = -2.1mv/c(typ), t0 = +25 ? c ? = ts v out tmin ?? v out tmax ?? C tmin tmax C --------------------------------------------------------------- ---------------- - = v out te ?? v out measured ?? v out equation1 ?? C v out equation1 ?? --------------------------------------------------------------- ---------------------------------------------- x100% = ts4 v out tmin ?? v out tmax ?? C tmin tmax C ?? --------------------------------------------------------------- ---------------- - m 255 = ?? ?? ?? v out tmin ?? v out tmax ?? C tmin tmax C ?? --------------------------------------------------------------- ---------------- - m0 = ?? ?? ?? C 255 ? =
isl21400 fn8091 rev 3.00 page 7 of 17 march 31, 2011 timing diagrams bus timing write cycle timing notes: (continued ) 15. temperature slope non- linearity is measured over the specif ied temperature range. the actual change in output voltage is s ubtracted from the expected change in output volt age, and then divided by the expe cted change to normalize before converting to percent. 16. for codes n = 8 to 255 17. guaranteed monotonic. 18. t wc is the time from a valid stop condition at the end of a write sequence of i 2 c serial interface, to the end of the self-timed internal nonvo latile write cycle. serial interface specification for scl, sda, a0, a1, a2 unless otherwise noted. (continued) symbol parameter test conditions min typ (note 2) max units tsnl t ? s y ? t ? ??? vout C ts y ? t ? --------------------------------------------------------- - x100%; y 123 ?? ==
isl21400 fn8091 rev 3.00 page 8 of 17 march 31, 2011 typical performance curves figure 1. v out vs temperature (a v = 1, 2) figure 2. v out vs temperature (a v = 4) figure 3. v out vs v cc (v cc = +2.7v to +5.5v) figure 4. supply voltage vs supply current figure 5. v out voltage noise (a v = 1, no load) figure 6. v out voltage noise (a v = 4, no load) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -40 -15 10 35 60 85 temperature (c) v ref (v) ts = 0 ts = 255 ts = 127 ts = 0 ts = 127 ts = 255 a v = 2 a v = 1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -40 -15 10 35 60 85 temperature (c) v ref (v) a v = 4 ts = 0 ts = 255 ts = 127 1.18 1.19 1.20 1.21 1.22 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) vref (v) v ref register = 255d ts register = 127d 0 2456 i cc (ma) +85c -40c 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 7 -40c v ref register = 255d ts register = 127d v cc (v) 3 +25c no load a v = 1 100v/div (v out x 1000) no load a v = 4 50v/div (v out x 1000)
isl21400 fn8091 rev 3.00 page 9 of 17 march 31, 2011 figure 7. accuracy vs temperature (-40c to +85c) figure 8. power-on figure 9. inl, v ref and temp slope dac figure 10. dnl, v ref and temp slope dac figure 11. v out vs v ref code (m) figure 12. v out vs temp sense code (n), t a = -40c and +85c typical performance curves (continued) 1.18 1.19 1.20 1.21 1.22 -40 -15 10 35 60 85 temperature (c) v ref (v) v ref register = 255d ts register = 127d ch2 = v out ch1 = v cc -3 -2 -1 0 1 2 3 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 code inl in lsb at +25c -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 code dnl in lsb at +25c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 v ref register code (m) v ref (v) at +25c ts register = 127d 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 0 15 30 45 60 75 90 105 120 135 15 0 165 180 195 210 225 240 255 v ref (v) +85c -40c v ref register = 255d ts register code (n)
isl21400 fn8091 rev 3.00 page 10 of 17 march 31, 2011 pin descriptions v out programmable voltage output p in. absolute voltage is determined by device temperat ure and equation 1. drive capability is limited to 500 a output curre nt and 5000pf output capacitance. a2, a1, a0 hardware slave addre ss pins that can be used to provide several isl21400 with a unique physical address to allow for multiple devices off one i 2 c bus. gnd this is the circuit ground pin. it is common for the v out and control signal inputs. sda serial data input/output. bidire ctional pin used for serial dat a transfer. as an output, it is o pen drain and may be wire-ored with any number of ope n drain or open collector outputs. a pull-up resistor is required and the value is d ependent on the speed of the serial data bus and the number o f outputs tied together. scl serial clock input. a ccepts a clock signal for clocking serial data into and out of the device. the scl line requires a pull-u p resistor whose value is dependen t on the speed of the serial clock bus and the number o f inputs tied together. v cc positive power supply. connect to a voltage supply in the range of 2.7v < v cc < 5.5v, with minimum noi se and ripple. for best performance, bypass with a 0.1f capacitor to ground. if the a v gain is set to 4 and v out approaches 5.0v, then v cc must be set to >5.2v for bes t output performance. functional description functional overview refer to the functional block diagram on page 2. the isl21400 provides a programma ble output voltage which combines both a temperature independent term and a temperature dependent term. t he temperature independent term uses a bandgap voltage ref erence, and th e temperature dependent term uses a proportional to absolute temperature (ptat) reference, or temperature sensor. each voltage source is scalable usin g two dacs via the i 2 c serial bus. the resulting output voltage can vary from 0v to over 5v and has a variable, programmable temperature slope (ts). reference sections referring to the block diagram on page 2, the v ref and temperature sense (v ts ) outputs are summed together ( ? ) and then passed through th e output gain stage (a). the voltage output is programmable and is determined by equation 1: where: ?a v = 1, 2, 4 ?v ref = 1.200 (not temperature dependent) ?0 ? n ? 255 (setting contain ed in register 0, v ref ) ?v ts = k(t - t 0 ) ? k = dv ts / dt = -2.1mv/c ? t = device temperature ?t 0 = +25c ?0 ? m ? 255 (setting contained in register 1, ts) see applications information on page 14 for ways to use equation 1 and metho ds for output volt age calculations. figure 13. v out vs i out (1ma) typical performance curves (continued) 1.200 1.201 1.202 1.203 1.204 1.205 1.206 1.207 1.208 1.209 -1 -0.5 0 0.5 1 i out (ma) v ref (v) v ref register = 255d ts register = 127d at +25c v out a v v ref n 255 --------- - ? v ts 2m ? ?? 255 C 255 -------------------------------- + ?? ?? ?? ? = (eq. 1)
isl21400 fn8091 rev 3.00 page 11 of 17 march 31, 2011 dacs section the isl21400 contains two 8-bit dacs whose registers can be programmed via the i 2 c serial bus. the dac registers are non-volatile such that the values are restored during the v cc power-up cycle of the d evice. one dac (v ref ) is dedicated to scale the bandgap voltage referenc e (temperature invariant) and the other dac (v ts ) is dedicated to scale the temperature sensor. both of these dacs can determine the output voltage as defined by equation 1 (see register descriptions). output gain amplifier section the isl21400 contains an output gain amplifier (a) that is programmed via the i 2 c serial bus. the gai n amplifier is the last stage before th e output and therefore controls the overall gain for the device. the gain can be programmed for 1x, 2x, or 4x amplification. this gain facto r is used to program the outpu t voltage as determined by e quation 1 (see register descriptions). there are 5 register s in the isl21400 devic e, all nonvolatile (see table 2). all registers are accessible for reading or writ ing through the i 2 c serial bus. register descriptions register 0: bandgap reference gain (nonvolatile) register 0 sets the output vol tage of the bandgap reference (v ref ). referring to equation 1, t he number n is the setting from register 0 as shown in equation 2: this term of equat ion 1 can vary from 0v to 1.20v. register 1: temperature slope gain (nonvolatile) register 1 sets the temperature slope (ts) of the temperature sensor. referring to equation 1, the number m is the setting from register 1 as shown in equation 3: v ts is the temperature depende nt term and varies from +136mv at -40c to -126mv at + 85c. the other term varies from -1 to +1 and scales the temperature term before adding to the v ref portion. register 2: device gain and storage (nonvolatile) register 2 contains 2 bits (2 lsbs) which control the output gain of the device. table 3 show s the state of these two bits and the resulting output gain. note that two states produce the same gain (gain 1:0 se t to 01b and 10b) of x2. the other 6-bits in the regist er can be used for general purpos e memory (nonvolatile) or left alone. registers 3 and 4: general purpose data (nonvolatile) these two registers are one byte each a nd can be used for general purpose nonvolatile memory. i 2 c serial interface the isl21400 supports a bidirect ional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receivi ng device as the receiver. the device controlling the transfer is the master and the device being controlled is the slave. t he master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl21400 operates as a slave device in all applications. table 1. isl21400 register bit map addr d7 (msb)d6d5d4d3d2d1 d0 (lsb) 0v ref 7v ref 6v ref 5v ref 4v ref 3v ref 2v ref 1v ref 0 1 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 2 d7d6d5d4d3d2gain1gain0 3 d7d6d5d4d3d2d1d0 4 d7d6d5d4d3d2d1d0 table 2. register descriptions reg nonvolatile description 0 y reference setting 1 y temperature sensor setting 2 y gain and storage 3 y storage 4 y storage v ref n 255 --------- - ? , for n = 0 to 255 (eq. 2) table 3. register 2 output gain (nonvolatile): output gain gain1 gain0 output gain, a v 00 x 1 01 x 2 10 x 2 11 x 4 v ts 2m ? ?? 255 C 255 -------------------------------- (eq. 3)
isl21400 fn8091 rev 3.00 page 12 of 17 march 31, 2011 all communication over the i 2 c interface is conducted by sending the msb of eac h byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop co nditions (see figure 10). on power-up of the isl21 400 the sda pin is in the input mode. all i 2 c interface operations m ust begin with a start condition, which is a high to low transition of sda while scl is high. the isl21400 continuou sly monitors the sda and scl lines for the start condi tion and does not respond to any command until this conditio n is met (see figure 10). a start condition is ignored during the power-up sequence and during non-volatile write cycles fo r the device. all i 2 c interface operations mus t be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 10) a stop condition at the end of a read operation, or at the end of a writ e operation plac es the device in its standby mode. a stop c ondition at the e nd of a write operation to a non-volatile byte initiates an internal non-vola tile write cycle. the device enters its standby state when the internal, non-volatile w rite cycle is completed. an ack, acknowledge, is a s oftware convention used to indicate a succe ssful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during t he ninth clock cycle, t he receiver pulls th e sda line low to acknowledge the reception of the eight bits of data (see figure 11). the isl21400 responds with an ack after recognition of a start condition followed by a va lid identification byte, and once again after successful receipt of an address byte. the isl21400 also responds with an ack after receiving a data byte of a write operation. t he master must r espond with an ack after receiving a data byte of a read operation. a valid identification byte c ontains 0101 a2 a1 a0 as the seven msbs. the a2 a1 a0 bits must correspond to the logic levels at those pins of the is l21400 device. the lsb in the read/write bit. its value is 1 for a read operation, and 0 for a write operation (see table 4). write operation a write operation requires a sta rt condition, followed by a valid identification byte, a valid address byte, a data byte, a nd a stop condition. after each o f the three bytes, the isl21400 responds with an ack. the master will then send a stop and at this time the device begins i ts internal non-volatile write cycle. during this time, the devi ce ignores transitions at the sda and scl pins, and the sda output is at a high impedance state. when the internal non-vola tile write cycle is completed, the isl21400 enters its standby state (see figure 12). stop conditions that terminate write operations must be sent by the master after sending at le ast 1 full data byte and its associated ack signal. if a sto p byte is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the isl21400 resets itself without performing the write. the contents of the array are not affected. data protection a valid identification byte, addre ss byte, and total number of scl pulses act as a protection for the registers. a stop condition also acts as a protect ion for non-volatile memory. during a write sequence, the da ta byte is loaded into an internal shift register as it is received. the presence of the stop condition after the rest o f the bits are received then triggers the non-volatile write. read operation a current address read operatio n is shown in figure 13. it consists of a minimum 2 bytes: a start followed by the id byte from the master with the r/w bit set to 1, then an ack followed by the data byte or by tes sent by the slave. the master terminates the read ope ration by not responding with an ack and then issuing a stop condition. this operation is useful if the master knows the current add ress and desires to read one or more data bytes. a random address read operation consists of a three byte dummy write instruction followed by a current address read operation (see figure 14). the ma ster initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to "0", an address byte, a second start, and a second identification byte with the r/w bit set to "1". after each of the three bytes, the is l21400 responds with an ack. the isl21400 then trans mits data bytes as long as the master responds with an ack duri ng the scl cycle following the eighth bit of each byte. the master terminates th e read operation (issuing a stop condition) following the last bit of the last data byte (see figure 13). the data bytes are from the regist ers indicated by an internal pointer. this pointer initials value is determined by the addr ess byte in the read operation inst ruction, and increments by one during transmission of each data byte. address 04h is the last valid data byte, higher addresses are not available. data from addresses higher than memory location 04h will be invalid. table 4. identification byte format 0 1 0 1 a2 a1 a0 r/w (msb) (lsb)
isl21400 fn8091 rev 3.00 page 13 of 17 march 31, 2011 sda scl start data data stop stable change data stable figure 14. valid data changes, start and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high high figure 15. acknowledge response from receiver figure 15. acknowledge response from receiver s t a r t s t o p identification byte with r/w = 0 address byte data byte a c k signals from the master signals from the isl21400 a c k 0 0 0 11 a c k write signal at sda 000 0 a0 a1 a2 00 0 figure 16. byte write sequence signals from the master signals from the slave signal at sda s t o p a c k 0 1 0 11 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k a2 a1 a0 read figure 17. address read sequence
isl21400 fn8091 rev 3.00 page 14 of 17 march 31, 2011 applications information power-up co nsiderations the isl21400 has on-chip eepr om memory storage for the dac and gain settings of the de vice. these settings must be recalled correctly on power-up fo r proper opera tion. normally there are no issues with recall, although it is always best to provide a smooth, glitch-free power-up waveform on v cc . adding a small 0.1f capacitor at the device v cc will help with power-up as well as v out load changes. noise performance the output noise voltage in a 0.1hz to 10hz bandwidth is typically 90v p-p . the noise measurement is made with a bandpass filter made of a 1-pole high-pass f ilter with a corner frequency at 0.1hz and a 2-pole low-pass filter with a corner frequency at 12.6hz to create a filter with a 9. 9hz bandwidth. load capacitance up to 5000pf can be add ed but will result in only marginal improvements in output noise and transient response. the output stage of the isl21400 is not designed to drive heavily capacitive loads . for high impedance loads, an r-c network can be added to fil ter high frequency noise and preserve dc control. output voltage programming considerations setting and controlling the out put voltage of the isl21400 can be done easily by breaking down the components into temperature variant and invariant, and setting them separately. lets use equation 1 to derive separate reference output and output temperature slope equations: the first term controls the out put dc value, and the second term controls the temperature slope, where dc output control discussion the reference term yields equa tion 4 for refe rence output: note that the dc term is depen dent on the 1.20v reference voltage, which is consta nt, the overall gain, a v , and the reference gain, a ref . since the product a v *a ref ranges from 0 to 4, the total referenc e dc output can range from 0.0v to 4.8v. in order to get the 4.8v output, v cc must be greater than 4.8v by the output dropout plus any overhead for output loading (the specification for v out = 5.0v is listed with v cc = 5.5v). the resolution of v out (dc) control changes with a v , so that with a 4.80v full scale output (a v = 4), the resolution is 4.80/255 or 18.8m v/bit. with a v = 1, the resolution is 4.7mv/bit. temp sense control discussion equation 4 yields this expression, equation 5, for temperature slope: since v ts = k(t - t 0 ), the slope term is dependent on the base temp slope of the device, k (-2.1mv/c), and the gain terms a v and a ts . this gives a formula (e quation 6) for t he portion of v out at a specific temperature: the product a v *a ts ranges from -4 to 4 , so the temperature slope can range from -8.4 to + 8.4mv/c, which is independent of the output dc voltage. the r esolution of slope control is determined by this range (8. 4mv/c) and the gain terms, and will vary from 65.8v/c/bit (a v = 4) down to 16.2v/c/bit (a v = 1). at t = t 0 = +25c, v out (ts) = 0, no changes in a ts will cause a change in v out , and v out will only va ry with the v out (dc) control. as temperature increases or decreases, from t = +25c, v out will then change according to the programmed temp slope. signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 00 0 11 s t o p a c k 0 1 0 11 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k a a a0 000 0 aaa figure 18. random address read sequence v out a v v ref ? n 255 --------- - ? ?? ?? ?? a v v ? ts 2m ? ?? 255 C 255 ---------------------------------- ?? ?? ? ?? ?? ?? + = a v v ref ? a ref ? ?? = a v v ? ts a ts ? ?? "" + reference term temp slope term + --------- - = (ranges from 0 to 1) a ts 2m ? ?? 255 C 255 ---------------------------------- ?? ?? (ranges from -1 to +1) = = v v ref ? a ref ? (eq. 4) v out ts ?? a v v ts ? a ts ? = (eq. 5) v out ts ?? a v k ? a ts ? tt 0 C ?? ? = (eq. 6)
isl21400 fn8091 rev 3.00 page 15 of 17 march 31, 2011 in many cases a form of equati on 6 is needed which yields a v out change with respect to temper ature. by rearranging, we get equation 7: example 1: programmed temperature compensation example the isl21400 can easily compensate for known temperature drift by programming the device for the initial v out setting and tempco using standard equations and some simple steps. the accuracy of the final programme d output will be limited to the data sheet specifications ( typically 1% accuracy for v out and slope). in this example, an n-channel mosfet gate has a -2.8mv/c tempco from -10c to +85c. a c onstant bias drain current is desired, with a target vgs range derived from the data sheet of 2.5v to 3.5v at +25c. offset setting : using equation 2 and targeting v out = 3.0vdc: note that a ref varies from 0 to 1, so to get 2.40, a v = 4. temperature slope setting : using equation 5, which can solve for slope directly: the isl21400 device can be programmed with these calculated parameters and perform temperature compensation or direct control in the target circuit. i f parameters change f or some reason, then the device ca n be reprogramm ed with new values and the circuit retested. example 2. calculating the v out temperature slope in some applications, it may be desirable to calculate what the output voltage and temp slope are, given the programmed register settings. su ch an application coul d be a closed loop system with internal calibrati on procedure. by reading the registers of the isl21400, then calculating the v out parameters, the system chara cteristics can be recorded. for the following example, lets determine the voltage output, v out (dc) at +25c, and also the change due to temperature variation (ppm) from +25c to +85c. equations 4 and 7 will be used to calculat e the answers. given, the contents of the registers: a v = 1 n = 178 decimal m = 74 decimal using equation 2: using equation 5: also, to solve for overall temp slope of the output: note that equation 1 can be us ed directly to solve for output voltage at a given tempera ture, in this case +85c: typical applications circuits ldmos rf power amplifier (rfp a). the isl21400 is used to set the gate bias for the ldmos transistor in a single stage of an rfpa. normally this is done with a dac or digital potentiometer with some discrete temperature compensation circuitry. the isl21400 simplifie s this control and allows a fu ll range of dc bias and tempco control. a typical circuit can be calibra ted for correct bias at room temperature (+25c) on power-up using a microcontroller or direct i 2 c control. the temperature of the unit can then be increased to the highest operat ing range, and the temperature slope setting can th en be adjusted to bring the amplifier back to correct bias. since the temp s lope setting has a negligible effect on the room temperature s etting, the amplifier will be biased correctly over the operat ing temperatur e of the unit. v out t ?? v out ts ?? tt 0 C ?? ----------------------------- = a v k ? a ts ? ,(in mv/ ? c ? = (eq. 7) v out dc ?? a v v ref ? a ref ? ?? = 3.00v = v ref 1.20v = a v a ref ? 2.50 = ?? 2.50 4 ----------- 0.625 n 255 --------- - == = n 159 decimal = 9f hex = ?? a v k ? a ts ? = 2.8mv ? c ? C = a ts 2.8 C 42.1 C ? -------------------- = a ts 0.333 2m ? ?? 255 C 255 ---------------------------------- == m 170 decimal = a9 hex = ?? a v v ref ? a ref ? ?? = 11.20 ? 178 255 --------- - ? ?? ?? = 0.8376v = ?? a v k ? a ts ? ?? mv ? c ? = 12.1 274 ? ?? 255 C 255 ------------------------------------ ? C ? = 0.8812mv ? c ? = ? c ? 872.5mv --------------------------------------- 10 6 ? 1010ppm ? c ? = --------- - ? 0.0021 C ?? 85 25 C ?? 274 ? ?? 255 C 255 --------------------------------- - + ?? ?? ?? ? v out a v v ref n 255 --------- - ? kt t 0 C ?? 2m ? ?? 255 C 255 -------------------------------- + ?? ?? ?? ? = v out +85 ? c ?? = 0.8905v = =
fn8091 rev 3.00 page 16 of 17 march 31, 2011 isl21400 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2006-2011. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. figure 19. ldmos rfpa bias control a2 +28v 1 2 3 u2 +5v regulator in out gnd i 2 c bus 5 6 1 2 3 8 7 1k r1 r2 100 c1 100pf c2 rf input q1 ldmos rf output sda scl a1 a0 vcc vout gnd +28v l1 a2 isl21400 4
isl21400 fn8091 rev 3.00 page 17 of 17 march 31, 2011 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x ? 4x ? gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - ? 0 o 6 o 0 o 6 o - rev. 2 01/03

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